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- VLSI architectures for high-speed MAP decoders.
VLSI Design 2001. Fourteenth International Conference on VLSI Design, (2002)
DOI: 10.1109/ICVD.2001.902698
https://ieeexplore.ieee.org/document/902698 - Design of low-power high-speed maximum a priori decoder architectures.
Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, (2002)
DOI: 10.1109/DATE.2001.915035
https://ieeexplore.ieee.org/document/915035 - Hardware/software trade-offs for advanced 3G channel coding.
Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition, (2002)
DOI: 10.1109/DATE.2002.998304
https://ieeexplore.ieee.org/document/998304 - Communication centric architectures for turbo-decoding on embedded multiprocessors.
2003 Design, Automation and Test in Europe Conference and Exhibition, (2003)
DOI: 10.1109/DATE.2003.1253634
https://ieeexplore.ieee.org/document/1253634 - Channel decoder architecture for 3G mobile wireless terminals.
Proceedings Design, Automation and Test in Europe Conference and Exhibition, (2004)
DOI: 10.1109/DATE.2004.1269229
https://ieeexplore.ieee.org/document/1269229 - Speculative disassembly of binary code.
CASES '16: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, (2016)
DOI: 10.1145/2968455.2968505
https://dl.acm.org/doi/10.1145/2968455.2968505 - A multi-standard channel-decoder for base-station applications.
SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design, (2004)
DOI: 10.1145/1016568.1016621
https://dl.acm.org/doi/10.1145/1016568.1016621 - Implementation comparisons of the QR decomposition for MIMO detection.
SBCCI '10: Proceedings of the 23rd symposium on Integrated circuits and system design, (2010)
DOI: 10.1145/1854153.1854204
https://dl.acm.org/doi/proceedings/10.1145/1854153 - FPGA implementation of parallel turbo-decoders.
SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design, (2004)
DOI: 10.1145/1016568.1016622
https://dl.acm.org/doi/10.1145/1016568.1016622 - A Multi-Level Monte Carlo FPGA Accelerator for Option Pricing in the Heston Model.
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, (2013)
DOI: 10.7873/date.2013.063
https://ieeexplore.ieee.org/document/6513509?arnumber=6513509